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Hi Timi,

I’ve read your many posts in lots of forum like verification academy etc.,
I’ve learned many things from your replies for people’s queries. Thanks a lot for your effort to help lots of beginners.

I’ve a query regarding writing constraint for AXI master address generation for below condition, it would be great if you give your comments!!!

1. Address should be size aligned for any transefer
2. Address should be Quad Word aligned if Data length is (<=) less than or equal to 2 Double
   Word (DW means 4 bytes here).
3. And it should satisfy the below expression,
   Address[1:0] + (length * (2burst_size)) <= 1 DW —(for one DW transfer)
   Address[2:0] + (length * (2burst_size)) <= 2 DW —(for <= 2DW transfer)

Please guide me to write constraints for these.!!

Thanks,
Ramesh

1 reply

TudorTimi Verification Gentleman

Could you ask this on StackOverflow?