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Welcome to Discourse
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1
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1001
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August 24, 2020
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A New Twist on SystemVerilog Enumerated Types
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14
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2465
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September 16, 2025
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Keeping Your Constraints in One Basket
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5
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1370
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May 12, 2024
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My Take on SVA Usage with UVM
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8
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2204
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February 17, 2024
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Do You Want Sprinkles with That? - Mixing in Constraints
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11
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1640
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January 19, 2024
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Custom Field Access Policies in UVM RAL
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9
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4726
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November 6, 2023
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Uvm report catcher functionality
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1
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1011
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September 10, 2023
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Establish UVM env with VIP
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1
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1215
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September 10, 2023
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Even More Ideas on Coverage Extendability
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8
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1169
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September 10, 2023
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A Subtle Gotcha When Using fork…join
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8
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1897
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September 10, 2023
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Starting sequence with start()
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1
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1566
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September 10, 2023
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Theory vs. Practice - Reserved Fields in UVM RAL
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9
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2017
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July 11, 2023
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Accessing pipelined transaction register
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0
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809
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February 14, 2023
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Can I start sequence with a virtual sequencer in a task?
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0
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1019
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February 13, 2023
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Driver using get and put
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1
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891
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January 29, 2023
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UVM based verification testbench for soc
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4
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3169
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January 21, 2023
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Rambling About UVM Factory Overrides - Per Instance
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8
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1454
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January 14, 2023
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Assertion Testvector
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2
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929
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January 8, 2023
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An Overview of UVM End-of-Test Mechanisms
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25
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7824
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December 12, 2022
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Fun and Games with CRV: Sudoku
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4
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1121
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November 28, 2022
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Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog
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9
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2239
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December 28, 2021
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Favor Composition Over Inheritance - Even for Constraints
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3
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1178
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November 22, 2021
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Goodbye Blogger, Hello Static Site
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6
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1179
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November 17, 2021
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Packages, Class Names and UVM
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18
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2689
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November 14, 2021
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The Not So Comprehensive Guide to SystemVerilog Array Constraints
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6
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1720
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October 18, 2021
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Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
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5
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1055
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November 14, 2021
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Accessing Multiple Registers at Once
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18
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3117
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November 14, 2021
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Fun and Games with CRV: The N-Queens Problem
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6
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1618
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November 13, 2021
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Drop Perl for Python in SVUnit
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5
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1142
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August 24, 2020
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What is SVUnit?
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0
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1161
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August 23, 2020
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