Assertion Testvector

SystemVerilog
1

I’m trying to understand assertion and made one simple example to test my assertion as the below

module asertion_ex;
  bit clk,a,b;

  always #5 clk = ~clk; //clock generation

  //generating 'a'
  initial begin
        a=1; b=1;
    #15 a=0; b=0;
    #10 a=1; b=0;
    #10 a=0; b=0;
    #10 a=1; b=1;
    #10;
    $finish;
  end

 a0:assert property
    (@(posedge clk) a |-> ##1 !b ##1 b ##1 !b);

//  //calling assert property
//  a_1: assert property(p);
    
  //wave dump
  initial begin

    $shm_open("wave.shm");
    $shm_probe("ASTF");
  end
endmodule

But I got failed

  (@(posedge clk) a |-> ##1 !b ##1 b ##1 !b);
                              |
xmsim: *E,ASRTST (./repetition1.sv,17): (time 15 NS) Assertion asertion_ex.a0 has failed (2 cycles, starting 5 NS)
    (@(posedge clk) a |-> ##1 !b ##1 b ##1 !b);
                                     |
xmsim: *E,ASRTST (./repetition1.sv,17): (time 35 NS) Assertion asertion_ex.a0 has failed (3 cycles, starting 15 NS)
Simulation complete via $finish(1) at time 55 NS + 0

I can’t understand why 5ns, 15ns has failed. This is Tool issue or Do I miss something?

2

The assigns can race with the clock. Try doing @(posedge clk) instead of #10.

1 Like
3

Thanks Timi
As your recommend, I found what is the problem.