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Welcome to Discourse
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1
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198
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August 24, 2020
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Driver using get and put
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3
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26
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February 1, 2023
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UVM based verification testbench for soc
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4
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23
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January 21, 2023
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Rambling About UVM Factory Overrides - Per Instance
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8
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183
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January 14, 2023
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Assertion Testvector
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2
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30
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January 8, 2023
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An Overview of UVM End-of-Test Mechanisms
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25
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661
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December 12, 2022
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Fun and Games with CRV: Sudoku
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4
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152
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November 28, 2022
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A New Twist on SystemVerilog Enumerated Types
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13
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295
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November 16, 2022
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Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog
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9
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393
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December 28, 2021
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Favor Composition Over Inheritance - Even for Constraints
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3
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276
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November 22, 2021
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Goodbye Blogger, Hello Static Site
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6
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173
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November 17, 2021
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Packages, Class Names and UVM
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18
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461
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November 14, 2021
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The Not So Comprehensive Guide to SystemVerilog Array Constraints
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6
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186
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October 18, 2021
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Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
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5
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130
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November 14, 2021
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Accessing Multiple Registers at Once
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18
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403
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November 14, 2021
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My Take on SVA Usage with UVM
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6
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327
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November 13, 2021
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Theory vs. Practice - Reserved Fields in UVM RAL
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8
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216
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November 13, 2021
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Fun and Games with CRV: The N-Queens Problem
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6
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253
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November 13, 2021
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Drop Perl for Python in SVUnit
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5
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348
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August 24, 2020
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What is SVUnit?
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0
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307
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August 23, 2020
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Of Copies and Clones
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9
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209
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November 13, 2021
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SystemVerilog 2012 Has Even More ‘Class’
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11
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196
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November 13, 2021
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Custom Field Access Policies in UVM RAL
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8
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414
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June 20, 2020
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On SystemVerilog Interface Polymorphism and Extendability
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11
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275
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November 13, 2021
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Testing SVA Properties and Sequences
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2
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143
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November 14, 2021
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Welcome to the Verification Gentleman Blog
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3
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174
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November 13, 2021
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Even More Ideas on Coverage Extendability
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6
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133
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November 13, 2021
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A Subtle Gotcha When Using fork…join
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6
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514
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November 14, 2021
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The Humble Beginnings of a SystemVerilog Reflection API
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9
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195
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November 14, 2021
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Registering Abstract Classes with the UVM Factory
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6
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314
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November 14, 2021
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