Establish UVM env with VIP

I’m writing this post to ask for your feedback as I’m planning a UVM verification environment and I’m stuck at one point.

My simple question is, if my DUT only has a bus interface, and I’m using VIP for verification, do I really need a local driver, sequencer, etc?

For example, assuming my “Timer_DUT” has only registers reg_A, reg_B, reg_C and an AHB interface, I can use the AHB VIP. The AHB VIP has all the other components implemented except for the scoreboard. However, this is only a VIP for the AHB control, not for the Timer_DUT, which means I thought I would need to create a sequence, sequence_item, driver, and monitor for the Timer_DUT.
However, since it is the AHB VIP that interfaces with the actual Timer_DUT, I don’t think the components that make up my Timer_DUT UVM env make sense other than the AHB agent.

For example, I know that my sequncer and Driver on the Timer_DUT are virtually meaningless in my UVM configuration if I need to enter some value in reg_A on the Timer_DUT and see what happens. I’m not sure how to just import the AHB VIP inside my UVM test class and manually test the behaviour as per the scenario.

So my question is, if a DUT consists of only bus protocols and is controlled by a VIP, do I need a driver or sequencer and if so, how would be a good way to configure it? Since the AHB driver is already implemented in VIP, what should I implement in my driver?

You’d need drivers/sequencers/monitors for the interfaces of your DUT. If you only have interfaces for which you already have VIPs, then there’s no need for any others.