SystemVerilog Constraints from Above

Hi Tudor,

Can you please solve follwing issue.
class base;
int aa;
endclass

class trn extends uvm_sequence_item;
base class_array[3];

rand int idx;
rand int aa_in_base;

function new (string name = “trn”);
super.new(name);
foreach(class_array[i]) begin
class_array[i] = new;
class_array[i].aa = i;
end
endfunction

constraint const_a {
idx == 1;
aa_in_base == class_array[idx].aa;
}
endclass

Randomization is failed…

unfortunately, my sim is failing in the test, when I randomize the seq because the constraint is accessing a null pointer (the transaction does not exist). I guess there is no automatic object creation. I have to create the transaction in the new() function of the sequence to avoid this error.