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About the Blog Comments category
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0
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235
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September 13, 2021
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My Take on SVA Usage with UVM
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8
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644
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February 17, 2024
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Do You Want Sprinkles with That? - Mixing in Constraints
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11
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416
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January 19, 2024
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Custom Field Access Policies in UVM RAL
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9
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953
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November 6, 2023
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Even More Ideas on Coverage Extendability
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8
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367
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September 10, 2023
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A Subtle Gotcha When Using fork…join
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8
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854
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September 10, 2023
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Theory vs. Practice - Reserved Fields in UVM RAL
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9
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556
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July 11, 2023
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Keeping Your Constraints in One Basket
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4
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376
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June 17, 2023
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Rambling About UVM Factory Overrides - Per Instance
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8
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492
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January 14, 2023
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An Overview of UVM End-of-Test Mechanisms
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25
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1531
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December 12, 2022
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Fun and Games with CRV: Sudoku
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4
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386
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November 28, 2022
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A New Twist on SystemVerilog Enumerated Types
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13
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720
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November 16, 2022
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Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog
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9
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808
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December 28, 2021
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Favor Composition Over Inheritance - Even for Constraints
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3
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477
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November 22, 2021
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Goodbye Blogger, Hello Static Site
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6
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414
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November 17, 2021
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Packages, Class Names and UVM
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18
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1004
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November 14, 2021
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The Not So Comprehensive Guide to SystemVerilog Array Constraints
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6
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454
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October 18, 2021
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Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
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5
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333
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November 14, 2021
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Accessing Multiple Registers at Once
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18
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813
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November 14, 2021
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Fun and Games with CRV: The N-Queens Problem
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6
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576
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November 13, 2021
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Of Copies and Clones
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9
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496
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November 13, 2021
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SystemVerilog 2012 Has Even More ‘Class’
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11
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526
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November 13, 2021
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On SystemVerilog Interface Polymorphism and Extendability
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11
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591
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November 13, 2021
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Testing SVA Properties and Sequences
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2
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324
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November 14, 2021
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Welcome to the Verification Gentleman Blog
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3
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337
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November 13, 2021
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The Humble Beginnings of a SystemVerilog Reflection API
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9
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476
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November 14, 2021
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Registering Abstract Classes with the UVM Factory
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6
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534
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November 14, 2021
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Fun and Games with CRV: The Zebra Puzzle
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9
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449
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November 13, 2021
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Enum fields in UVM_REG
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3
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325
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November 13, 2021
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SystemVerilog Constraints from Above
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21
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958
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November 13, 2021
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