UVM based verification testbench for soc

1

Hi Tudor and All.
I’m trying to get some idea for AHB based UVM Verification with a very small ARM Cortex-M3 SoC architecture.

Here’s my example M3 architecture.

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As you can see that attached image, there are 2 memory and 1 GPIO slaves.

If I want to verify a GPIO slave by using an AHB VIP(such as GitHub - GodelMachine/AHB2: AMBA AHB 2.0 VIP in SystemVerilog UVM) then How do I verify the GPIO DUT Slave?

There is a very simple firmware also in. So I can’t remove the whole system except AHB to APB bridge and GPIO DUT Slave. I should verify the GPIO dut slave with CPU.

I thought that I would need to make a Slave port in the BUS Matrix(cmsdk_ahb_busmatrix) for verification only? but I’m not sure about this. Could you please guide me how to verify the GPIO DUT Slave such as this architecture?

2

If you have to keep the CPU in, there’s not much chance of using the AHB VIP here for anything GPIO related. Sounds like you have to write all your tests in C/assembly.

3

Thanks Tudor,

Maybe I think I have to remove the CPU then replace it with agent acting as CPU.
Could you give some Idea if I remove the CPU then what the best general solution do?

4

Why don’t you just make a TB around the GPIO block, if this is what you’re testing? Alternatively you can force the outputs of the CPU to be driven by an AHB agent. This is what I’d do if the focus is more on the connections between the blocks.

5

Yes. That’s make a sense to me. Thanks for advice.