I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.
This is a companion discussion topic for the original entry at https://verificationgentleman.netlify.app/2020/11/24/comparison-of-formal-and-simulation-part-1.html