I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest of the (class-based) testbench to stay timing agnostic. Since assertions are a key part of the checking infrastructure we need to make sure that they're bulletproof. This means that we need to test them to make sure that they're doing what we expect them to do.
Thank you for the thorough review.
We have planned several framework updates, including some that you have pointed out (e.g. UVM dependencies).
We value your feedback and suggestions and intend to keep SVAUnit up-to-date.
I’ve updated the post after publishing. While writing, I noticed that I used some crazy inverted logic when reasoning about the test pass/fail criteria (i.e. using “fail_if_" instead of "pass_if_”. I also added a link to the example code.
The fact that it relies on UVM is a plus for me. This made it easier for me to integrate into our environment, without having to learn some other framework.
If something needs a framework, it might as well be UVM.
Note about your interface: always #1 CLK = ~CLK;
This will not toggle. The following would toggle: always #1 CLK <= ~CLK;
Due to a VCS bug that should be fixed soon, I prefer to use: define CYCLE 10 logic CLK; initial begin CLK <= '0; forever #(CYCLE/2) CLK = ~CLK;
end
I will be explaining this code and other time-0 race conditions and other verification timing issues in an Austin SNUG paper at the end of September, 2016
Regards- Cliff Cummings