Quite a while back I wrote a series of posts about coverage extensibility in SystemVerilog. In the first post we looked at how to use policy classes to implement extensible coverage collectors, where ignore bins can be tweaked via class parameters. The second post explored a dynamic flavor of this approach, using constructor arguments instead. Finally, the third post tied everything together by looking at how these approaches interact with UVM and the factory.
This is a companion discussion topic for the original entry at https://blog.verificationgentleman.com/2026/03/01/coverage-extensibility-in-systemverilog-2023.html