I'll be giving a talk this week at DVCon Europe about how to use the UVM REG classes to verify memory sub-systems. In particular, I'll focus on how to translate from abstract memory burst accesses (the kind started by calling uvm_mem::burst_read/write(...)) to bus transactions. This isn't as easy as translating register accesses where an adapter is enough, mainly because an adapter can't process accesses that are bigger than the underlying bus width.
The talk went ok, but not stellar (mostly, I guess, because it wasn’t a topic of general interest). The proceedings should be available online sometime soon. I’ll post a link when they are.
One small hint: You can pull the unifications directly into the head, shortening your code a bit and making it immediately clear what the argument is:
gen_mem_burst(mem_burst(Len, Bursts)) :-
…
Actually, you can also improve the name, since this predicate can not only be used to generate, but also to test the argument. So mem\_burst/1 would be a nice declarative name for a predicate that works in several directions.