My Take on SVA Usage with UVM

For verifying complex temporal behavior, SystemVerilog assertions (SVAs) are unmatched. They provide a powerful way to specify signal relationships over time and to validate that these requirements hold. One limitation of SVAs is that they can only be used in static constructs (module, interface or checker). Since modern verification is class based, this leads to segregation between the assertions and the testbench. There have been many papers written about how to bring these two parts of the verification environment closer together, particularly when using UVM.

This is a companion discussion topic for the original entry at

Can you please give sample test example to work with?
it will be a great help.

You can download the code here:

Hi, While using virtual interface get inside test to use $assertoff - questa runs into following error
runtime “Illegal virtual interface dereference”

As mentioned in the post, this doesn’t generally work, hence the need to put more effort into disabling the assertion.

Yeah, If I call assertoff from top module of tb , it’s working fine. Thanks