Temporary Variables in SystemVerilog Procedural Blocks

It is a well known fact that inside a procedural block variables can only be defined at the very beginning. Say you would have the following code:

This is a companion discussion topic for the original entry at https://verificationgentleman.netlify.app/2014/06/15/temporary-variables-in-systemverilog.html

As a side note, when you find yourself wanting to declare such a begin…end block, it might also be time to consider spinning out that piece of code as an own method.