My name is Tudor Timisescu. I am a Verification Engineer at Infineon Technologies, where I verify cryptographic co-processors and develop in house verification IP. While I mainly work with SystemVerilog and e, I also dabble in other topics such as formal verification, VPI applications, automation tools and more.
I’ve read your many posts in lots of forum like verification academy etc.,
I’ve learned many things from your replies for people’s queries. Thanks a lot for your effort to help lots of beginners.
I’ve a query regarding writing constraint for AXI master address generation for below condition, it would be great if you give your comments!!!
Address should be size aligned for any transefer
Address should be Quad Word aligned if Data length is (<=) less than or equal to 2 Double
Word (DW means 4 bytes here).
And it should satisfy the below expression,
Address[1:0] + (length * (2burst_size)) <= 1 DW —(for one DW transfer)
Address[2:0] + (length * (2burst_size)) <= 2 DW —(for <= 2DW transfer)