A feature where SystemVerilog really shines for hardware verification is its assertion language. Making it easy to specify complex requirements in a clear and easily understandable way, coupled with the fact that they can be used for both simulation and formal verification, means that SVAs are the complete package.
This is a companion discussion topic for the original entry at https://verificationgentleman.netlify.app/2014/05/03/are-you-implying-overlapped-implication.html