|
Testing UVM Drivers, Part 2
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6
|
1567
|
November 14, 2021
|
|
A Quick Look at SVAUnit
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6
|
1369
|
November 14, 2021
|
|
Some More Ideas on Coverage Extendability
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3
|
1012
|
November 13, 2021
|
|
UVM Drain Time - The Old Fashioned Way
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15
|
3495
|
November 14, 2021
|
|
The Humble Beginnings of a SystemVerilog Reflection API, Part 3
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3
|
861
|
November 14, 2021
|
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How Do I Transfer Thee? Let Me Count the Ways
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6
|
1181
|
November 13, 2021
|
|
Fun and Games with CRV: Einstein’s Puzzle (Revisited)
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2
|
885
|
November 14, 2021
|
|
On SystemVerilog Coding Conventions - Challenging the Status Quo
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14
|
3147
|
November 13, 2021
|
|
Be More Assertive about Your Testbench Code
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6
|
1577
|
November 13, 2021
|
|
Some Ideas on Coverage Extensibility
|
|
2
|
1111
|
November 13, 2021
|
|
Rambling About UVM Factory Overrides - Per Type
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14
|
2413
|
November 13, 2021
|
|
Keeping Constraints and Covergroups in Sync
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5
|
1738
|
November 13, 2021
|
|
Cooking at Home or Eating Out? - The Pros and Cons of Homegrown VIP
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7
|
1076
|
November 13, 2021
|
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Fun and Games with CRV: Draw This Without Lifting Your Pencil
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4
|
992
|
November 13, 2021
|
|
Patching a Leaky Boat - Handling UVM Bugs
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8
|
1191
|
November 13, 2021
|
|
Less Is More - Why I Favor Short Tests
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3
|
830
|
November 13, 2021
|
|
Temporary Variables in SystemVerilog Procedural Blocks
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2
|
872
|
November 13, 2021
|
|
Using indirect_access(…) in vr_ad
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4
|
914
|
November 13, 2021
|
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Working with Multiple Instances of vr_ad Registers
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4
|
1137
|
November 13, 2021
|
|
Experimental Cures for Flattened Register Definitions in vr_ad
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3
|
910
|
November 13, 2021
|