|
Testing UVM Drivers, Part 2
|
|
6
|
1502
|
November 14, 2021
|
|
A Quick Look at SVAUnit
|
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6
|
1255
|
November 14, 2021
|
|
Some More Ideas on Coverage Extendability
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|
3
|
939
|
November 13, 2021
|
|
UVM Drain Time - The Old Fashioned Way
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|
15
|
3267
|
November 14, 2021
|
|
The Humble Beginnings of a SystemVerilog Reflection API, Part 3
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|
3
|
821
|
November 14, 2021
|
|
How Do I Transfer Thee? Let Me Count the Ways
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|
6
|
1107
|
November 13, 2021
|
|
Fun and Games with CRV: Einstein’s Puzzle (Revisited)
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|
2
|
851
|
November 14, 2021
|
|
On SystemVerilog Coding Conventions - Challenging the Status Quo
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|
14
|
2981
|
November 13, 2021
|
|
Be More Assertive about Your Testbench Code
|
|
6
|
1466
|
November 13, 2021
|
|
Some Ideas on Coverage Extensibility
|
|
2
|
927
|
November 13, 2021
|
|
Rambling About UVM Factory Overrides - Per Type
|
|
14
|
2289
|
November 13, 2021
|
|
Keeping Constraints and Covergroups in Sync
|
|
5
|
1683
|
November 13, 2021
|
|
Cooking at Home or Eating Out? - The Pros and Cons of Homegrown VIP
|
|
7
|
1011
|
November 13, 2021
|
|
Fun and Games with CRV: Draw This Without Lifting Your Pencil
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|
4
|
932
|
November 13, 2021
|
|
Patching a Leaky Boat - Handling UVM Bugs
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|
8
|
1119
|
November 13, 2021
|
|
Less Is More - Why I Favor Short Tests
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|
3
|
796
|
November 13, 2021
|
|
Temporary Variables in SystemVerilog Procedural Blocks
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|
2
|
834
|
November 13, 2021
|
|
Using indirect_access(…) in vr_ad
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|
4
|
869
|
November 13, 2021
|
|
Working with Multiple Instances of vr_ad Registers
|
|
4
|
1084
|
November 13, 2021
|
|
Experimental Cures for Flattened Register Definitions in vr_ad
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|
3
|
874
|
November 13, 2021
|